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CXA1202Q-Z/CXA1202R
REC/PB Amplifier for VCR For the availability of this product, please contact the sales office.
Description CXA1202Q-Z/CXA1202R are bipolar ICs developed as REC/PB amplifiers for VCR's. Features * Built-in head amplifier feedback dumping contributes to the reduction of external components and simplification of the print circuit board design. * Built-in BPF for PB signals medium range frequency compensation totally eliminates external resonance circuits (L. C. R.) * Low range recording signal variable-level mix amplifier allows for both metal powder and metal evaporated tapes application. * Consumption saving through power save function of the REC AMP. * 4-head system switch incorporated. Functions * Recording: 2-channel REC AMP, 5-input (Y, Chroma, AFM, ATF, PCM) Mix AMP. * Playback: 2-channel low-noise head amplifier, medium range frequency compensation circuit, RF AGC, dropout detecting circuit. Structure Bipolar silicon monolithic IC Applications * 8-mm system VCR * -system VCR * VHS-system VCR Absolute Maximum Ratings (Ta = 25C) * Supply voltage Vcc 8 V * Operating temperature Topr -10 to +75 C * Storage temperature Tstg -55 to +150 C * Allowable power dissipation PD (CXA1202Q-Z) 920 mW PD (CXA1202R) 1100 mW (CXA1202R: Substrate area 40 x 25mm2, t = 0.635mm when ceramic print circuit board mounted) Recommended Operating Condition Supply voltage Vcc CXA1202Q-Z 48 pin QFP (Plastic) CXA1202R 48 pin LQFP (Plastic)
5 0.25
V
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E88012-PS
CXA1202Q-Z/CXA1202R
Block Diagram and Pin Configuration
REC2 OUT
PB IN 2N
PB IN 1N
PB IN 2P
PB IN 1P
REC1 OUT
VCC 2CH
VCC 1CH
REC2 IN
36
35
34
33
32
31
30
29
28
27
26
MT F
25
MIX2 OUT 37 MT 2 38
CH2 REC AMP 46dB
CH1 REC AMP
REC1 IN
MT Q
24 MIX1 OUT 23 MT1
RF SWP 39 GND 2CH 40 PCM SEL 41 ME LEVEL 42 GND REC 43 ATF LEVEL 44 RP PB 1CH 45 ATF IN 46 RP PB 2CH 47 6dB PCM IN 48 CONTROL LOGIC
CH2 HEAD AMP 9dB
46dB
CH1 HEAD AMP 9dB
22 MULTI 21 GND 1CH 20 V RF OUT
MTF MTQ Video -6dB CH2 SW CH1 Mute
VP1 VP2 -6dB SW SW PV PV
19 GND PB 18 DOC IN 17 VCC EF 16 RF OUT
BPF
BPF
VCA MT2
MT1
VCA 6dB CH1 GCA 12dB DOC DET A B RF SW 15 DOC TC 14 RF IN B 13 DOC PULSE DOC DET
Medium range freq. compensation
VCA
ME LEVEL ATF SW Normal VCA Multi
CH2 PCM MIX SW AMP 6dB VCA
RF DET AGC
1
2
3
4
5
6
7
8
9
10
11
12
RP PB EN
PCM RF OUT
AGC OUT
AGC TC
AFM IN
HCHG
VREG
Y IN
VCC
VG
-2-
RF IN A
C IN
CXA1202Q-Z/CXA1202R
Pin Description Voltage No. Symbol DC AC
I/O resistance
Equivalent circuit
VCC
Description
1
1
(Open: RP PB EN "L")
--
40k
40k
Power-save recording at Low. High: over 3V Low: under 1V
GND VCC
20k
2
2
C IN
3.2V
134 mVp-p
20k
20k 100
Input pin for Chroma signal.
GND VCC 24k
3
VREG
4.2V
--
--
3 35k
Output pin for VREG 4.2V. Decoupling with capacitance.
GND
4
AFM IN
3.2V
80 mVp-p
20k
Same as for Pin No. 2
VCC 150
Input pin for AFM signal.
5
VG
2.5V
--
--
5 2.5k GND
Output pin for virtual GND. Decoupling with capacitance.
6 7
Y IN Vcc
3.2V 5.0V
250 mVp-p --
20k --
Same as for Pin No. 2 --
VCC 440
Input pin for Y signal. Supply pin for circuits other than REC AMP and Head AMP.
8
PCM RF OUT
1.8V
50 to Emitter 500 follower mVp-p (IE = 1mA)
1mA
8
Output pin for PB PCM signal.
GND
-3-
CXA1202Q-Z/CXA1202R
Voltage No. Symbol DC AC
I/O resistance
Equivalent circuit
VCC 500 200
Description
9
AGC TC
4.25V (Load: 150k
9
200
--
--
Pin to apply time constant of envelope detection for RF AGC. Optimum load resistance across Vcc is 150k.
GND
VCC 200 17
10
AGC OUT
2.5V
Emitter 100 follower mVp-p (IE = 1mA)
10
AGC output pin for PB VIDEO signal (Max. gain of AGC AMP is about 7dB).
1mA GND VCC
11
HCHG
-- (Open: "L")
--
50k
50k 11
Control signal input pin for RF SW switching: High (over 3V): selects RF IN A Low (under 0.3V): selects RF IN B
GND VCC
150
12
RF IN A
2.5V
100 mVp-p
12
--
20k 5 GND VCC 100
Input pin for RF switch and 12dB AMP.
13
DOC PULSE
H: 3.2V L: 0V
--
Emitter follower (H: IE = 1mA)
13 80k 3.5k GND
Dropout detection signal output pin; High upon dropout.
14
RF IN B
2.5V
100 mVp-p
20k
Same as for Pin No. 12
VCC 90 8k 3.3k 15
Input pin for RF switch and 12dB AMP.
15
DOC TC
2.5V
--
--
Pin to connect time constant of dropout detection.
GND
-4-
CXA1202Q-Z/CXA1202R
Voltage No. Symbol DC AC
I/O resistance
Equivalent circuit
VCC 200
Description
16
RF OUT
2.5V
Emitter 400 follower mVp-p (IE = 500A)
500A
16
Output pin of signal selected by HCHG from RF IN A and RF IN B.
GND VCC
17
17
Vcc EF
5.0V
--
--
200
Supply pin for emitter followers of AGC OUT, DOC TC and RF OUT.
GND VCC 150
18
DOC IN
2.5V
400 mVp-p
18
8k
8k 2.5V GND
Input pin for dropout detection.
19
GND PB
0V
--
--
--
VCC 400
GND pin for medium range frequency compensation circuit, RF AGC and DOC DET.
20
V RF OUT
1.8V
Emitter 50 to follower 500 (IE = mVp-p 500A)
20
Output pin for PB VIDEO signal.
500A
GND
21
GND 1CH
0V -- (OPEN: "L") -- (2.5V at OPEN of pin)
--
--
--
GND pin for CH1 REC AMP and CH1 Head AMP. Multi-channel PCM REC mode at High.
22
MULTI
--
40k
Same as for Pin No. 1
VCC 25k
23
MT1
--
100k
23
47k
53k 5 GND
Boost level adjusting pin for CH1 medium range frequency compensation circuit. Variable between 0 and +12dB at 4.2 to 0.8V.
-5-
CXA1202Q-Z/CXA1202R
Voltage No. Symbol DC AC
I/O resistance
Equivalent circuit
VCC 400
Description
24
MIX1 OUT
2.5V
Emitter 203 follower mVp-p (IE = 1mA)
1mA
24
Mix circuit output pin for CH1.
GND VCC
100
25
REC1 IN
1.8V
92A (Y signal)
~0 -
25 100 200
CH1 REC AMP input pin.
GND VCC
26
MT F
2.5V
--
--
26 90
GND
F adjusting pin for medium range frequency compensation circuit; F is controlled through current value by connecting resistance between GNDs. Mutually affected by MT Q. Do not connect capacitance. Power supply pin for CH1 REC AMP and CH1 Head AMP.
27
Vcc 1CH
5.0V
--
--
--
28
28
REC1 OUT 15mA
13 Open mAp-p collector
CH1 REC AMP output pin.
20 GND
VCC 29
29
PB IN 1P
2.4V
90 to 900 Vp-p
1.3k
10k GND VCC
CH1 head AMP positive phase input pin (PB signal input pin).
30
PB IN 1N
2.4V
--
1.3k
30
CH1 Head AMP inverter phase input pin (decoupling with capacitance).
GND
-6-
CXA1202Q-Z/CXA1202R
Voltage No. Symbol DC 2.4V AC -- 90 to 900 Vp-p 13 mAp-p --
I/O resistance
Equivalent circuit
Description CH2 Head AMP Inverter phase input pin (decoupling with capacitance). CH2 Head AMP positive phase input pin (PB signal input pin). CH2 REC AMP output pin. Power supply pin for CH2 REC AMP and CH2 Head AMP. Q adjusting pin for medium range frequency compensation circuit. Controls Q through current value by connecting resistance between GNDs; Mutually effected by MT F. Do not connect capacitance. CH2 REC AMP input pin.
31
PB IN 2N
1.3k
Same as for Pin No. 30
32
PB IN 2P
2.4V
1.3k
Same as for Pin No. 29
33 34
REC2 OUT 15mA Vcc 2CH 5.0V
Same as for Pin No. 28 -- --
35
MT Q
2.5V
--
--
Same as for Pin No. 26
36
REC2 IN
1.8V
92A (Y signal)
~0 -
Same as for Pin No. 25
37
MIX2 OUT
2.5V -- (2.5V at OPEN of pin) -- (Open: "L") 0V
Emitter 203 follower mVp-p (IE = 1mA)
Same as for Pin No. 24
Mix circuit output pin for CH2.
38
MT 2
--
100k
Same as for Pin No. 23
Boost level adjusting pin for CH2 medium range frequency compensation circuit; variable between 0 and +12dB at 4.2 to 0.8V. RF switching pulse input pin for CH switchover. GND pin for CH2 REC AMP and CH2 head AMP. PCM AREA input pin; High: PCM REC period During High period after recording, MUTE is applied to PB VIDEO output.
39
RF SWP
--
40k
Same as for Pin No. 1
40
GND 2CH
--
--
--
41
PCM SEL
-- (Open: "L")
--
40k
Same as for Pin No. 1
VCC
42
-- (2.1V ME LEVEL at OPEN of pin)
2.1V
--
18k
100k
24k 76k
42
Level of low range REC signals (Chroma, AFM, ATF rec. with VIDEO) can be boosted by 0 to 3dB by voltage (0 to 5V) applied to this pin.
GND
-7-
CXA1202Q-Z/CXA1202R
Voltage No. 43 Symbol GND REC DC 0V -- (2.1V at OPEN of pin) AC --
I/O resistance
Equivalent circuit --
Description GND pin for VG, VREG, LOGIC and mix circuit. REC Ievel of ATF signal can be boosted by 0 to 3dB by the voltage (0 to 5V) applied to this pin. In multi PCM mode, priority given to 6dB AMP. REC/PB switchover signal for CH1: High: PB Low: REC However, when RP PB EN pin is at Low: High: power save REC Low: REC
--
44
ATF LEVEL
--
100k
Same as for Pin No. 42
45
RP PB 1CH
-- (Open: "L")
--
40k
Same as for Pin No. 1
VCC
46
ATF IN
2.5V
250 mVp-p
100
20k
46 20k 5 GND
Input pin for ATF pilot signal.
47
RP PB 2CH
-- (Open: "L")
--
40k
Same as for Pin No. 1
REC/PB switchover signal for CH2: High: PB Low: REC However, when RP PB EN pin is at Low: High: power save REC Low: REC Input pin for PCM signal.
48
PCM IN
3.2V
250 mVp-p
20k
Same as for Pin No. 2
-8-
Electrical Characteristics (Ta = 25C, Vcc = 5V, See the Electrical Characteristics Test Circuit.) Test conditions Input condition Test method Min. Typ. Input pin Level
Test point, Ammeter Control Other 1 SW ON name Frequency logic
No.
Item
Symbol
Max.
Unit

1 A 42, 44 24 37 24 B 37 24 5MHz 37 1MHz E J K K 37 750kHz D 24 At min. gain of 0V at ME LEVEL pin F 37 24 37 24 5MHz 10MHz Ievel 1MHz Ievel 24 C 10MHz Ievel 1MHz Ievel IVCC
REC mode circuit current 20.5
IREC
In both CH REC, internal consumption current (excluding REC output current) -2.6
27.5
35.0
mA
CH1 GY1 6 1MHz A 250 mVp-p 250 mVp-p 10MHz 1MHz
2
Mix AMP Y gain 6
-1.8
-1.0
dB
CH2 GY2
CH1 VFY1
3
-1.0
-0.2
dB
Mix AMP Y frequency response 6 500 mVp-p 250 mVp-p
CH2 VFY2
-9- 48 48 250 mVp-p 10MHz 1MHz 48 2 500 mVp-p 150 mVp-p
4
Mix AMP CH1 DY1 Y secondary distortion factor CH2 DY2
-50
-40
dB
5
Mix AMP PCM gain
CH1 GP1
-2.8
-1.8
-0.8
dB
CH2 GP2
6
Mix AMP CH1 VFP1 PCM frequency CH2 VFP2 response
-1.0
-0.2
dB
7
Mix AMP CH1 DP1 PCM secondary distortion factor CH2 DP2
-50
-40
dB
8
Mix AMP Chroma gain
GC1
-12.7 -11.7
-10.7
dB
CXA1202Q-Z/CXA1202R
1 See the Control Logic Truth Table for control logic conditions.
(Ta = 25C, Vcc = 5V, See the Electrical Characteristics Test Circuit.) Test conditions Input condition Test method Typ. Max. Min. Input pin Level D 2 24 E 42 150 mVp-p 750kHz 2.4 Change in gain when ME LEVEL pin is brought from 0 to 5V 3.4
Test point, Ammeter Control Other 1 SW ON name Frequency logic
No.
Item
Symbol
Unit
9
Mix AMP Low range freq. (Chroma, AFM, GME ATF rec. with VIDEO) variable gain by ME LEVEL pin 2 K 24 250 mVp-p 750kHz 42 100 mVp-p 1.5MHz D 37 250 mVp-p 1.5MHz F 37 42 At max. gain of 5V at ME LEVEL pin At min. gain of 0V at ME LEVEL pin At max. gain of 5V at ME LEVEL pin -50
4.4
dB
10
Mix AMP Chroma secondary distortion factor 4
DCI
-40
dB
11
Mix AMP AFM gain 4
GAF1
-11.2 -10.1
-9.0
dB
- 10 - 46 J 37 250 mVp-p 100kHz 46 J 250 mVp-p 100kHz 24 46 J 44 250 mVp-p 100kHz 37 46 250 mVp-p 100kHz J 42 24
12
Mix AMP AFM secondary distortion factor
DAF1
-50
-40
dB
13
Mix AMP ATF gain (rec. with VIDEO)
GATV
At min. gain of 0V at both ME LEVEL pin and ATF -28.9 -27.6 LEVEL pin At min. gain of 0V at both ME LEVEL pin and ATF -28.9 -27.6 LEVEL pin Change in gain when ATF LEVEL pin is brought from 0 to 5V 2.4 3.4
-26.3
dB
14
Mix AMP ATF gain (rec, with PCM)
GATP
-26.3
dB
15
Mix AMP ATF variable gain by ATF LEVEL pin
GATA
4.4
dB
16
Mix AMP ATF rec. with PCM variable gain by ME LEVEL pin
GATM
Change in gain when ME LEVEL pin is brought from 0 to 5V
2.3
3.3
4.3
dB
CXA1202Q-Z/CXA1202R
1 See the Control Logic Truth Table for control logic conditions.
(Ta = 25C, Vcc = 5V, See the Electrical Characteristics Test Circuit.) Test conditions Input condition Test method Min. Max. Typ. Input pin Level J 100kHz G IREC1 A IREC2 25 28 1MHz F 33 28 1MHz F 33 28 B 33 28 5MHz E 33 -49 -40 dB 10MHz 1MHz Output level [V] 100 [] 36 25 36 25 36 25 36 300 mVp-p 200 mVp-p 200 mVp-p 200 mVp-p 12.0 13.2 14.4 mA p-p DC current testing 13.4 15.7 18.0 mA 24 4.9 5.9 250 mVp-p Change in gain when control logic is set to multi PCM 6.9 46
Test point, Ammeter Control Other 1 SW ON name Frequency logic
No.
Item
Symbol
Unit
17
Mix AMP ATF gain increment at multi PCM
GATMU
dB
CH1 IDR1
18
REC AMP output bias current
CH2 IDR2
CH1 IR1
19
REC AMP output bias current
CH2 IR2
20
REC AMP channel balance
VR21
Difference in output level between CH1 and CH2
-0.8
0.0
0.8
dB
- 11 - 29 H 1MHz I I 1MHz H H 32 29 32 29 200 Vp-p 200 Vp-p 5MHz 200 Vp-p 23 38 23 38 23 8 20 10
CH1 VFR1
21
REC AMP frequency response
CH2 VFR2
10MHz Ievel 1MHz Ievel
-3.2
-2.1
dB
22
REC AMP CH1 DR1 secondary distortion factor CH2 DR2
52.2 54.5 57.2 dB
CH1 GV1
23
Head AMP VRF OUT gain
CH2 GV2
CH1 GP1
24
52.2
54.5
57.2
dB
Head AMP PCM RF OUT gain
CH2 GP2
25
AGC OUT Ievel
VAGC
70
95
120
mV p-p
CXA1202Q-Z/CXA1202R
1 See the Control Logic Truth Table for control logic conditions.
(Ta = 25C, Vcc = 5V, See the Electrical Characteristics Test Circuit.) Test conditions Input condition Test method Min. Typ. Max. Input pin Level 900 Vp-p 29 200 Vp-p 100 Vp-p 29 200 Vp-p Output level at input 200V H 1MHz 10 I HJ 23 10 38 11 16 1MHz IJ H 300kHz I J K H 11 18 11 10MHz 300kHz 16 10MHz Ievel 300kHz Ievel -2.0 -0.4 dB 38 23 100 Vp-p 900 Vp-p 100 Vp-p 5MHz H 10 23 Output level at input 100V 5MHz H 10 23 Output level at input 900V Output level at input 200V -0.3 0.5
Test point, Ammeter Control Other 1 SW ON name Frequency logic
No.
Item
Symbol
Unit
26
AGC control characteristics "H"
VAGCH
1.3
dB
27
AGC control characteristics "L"
VAGCL
-0.8
-0.1
0.6
dB
29 32 29 32 12 14 12 14 12 See the following figure 2 100 mVp-p 100 mVp-p
28
DC offset between channels CH1 - CH2
VDC12
DC voltage testing At CH1 Low input - at CH2 High input At CH2 High input - at CH1 Low input Difference of DC voltage at logic switchover
-60
0
60
mV
- 12 -
29
DC offset at MUTE, CH1, CH2 - MUTE
VDCM
-60
0
60
mV
A input GRFA
30
RF SW gain
11.1
12.1
13.1
dB
B input GRFB
A input VFRFA
31
RF SW frequency response
B input VFRFB
32
Dropout detection, ON level
VD ON
Pin 18 Ievel when DOC PULSE pin becomes High -16.5 -13.0 (0dB = 400mVp-p)
-10.5
dB
CXA1202Q-Z/CXA1202R
1 See the Control Logic Truth Table for control logic conditions.
(Ta = 25C, Vcc = 5V, See the Electrical Characteristics Test Circuit.) Test conditions Input condition Test method Min. Max. Typ. Input pin Level see the figure below 2 I 18 0.0 3.1 30.0 3.2 40.0 11 -7.0 100 mVp-p 5MHz H 13 DC voltage testing DC voltage testing Current consumption with both CHS in PB 13 IVCC H H 11 11 Pin 18 Ievel when DOC PULSE pin becomes Low -9.5 (0dB = 400mVp-p) 12
Test point, Ammeter Control Other 1 SW ON name Frequency logic
No.
Item
Symbol
Unit
33
Dropout detection, OFF Ievel 12
VD OFF
-5.0
dB
34
Dropout pulse, Low level
VPDL
0.1 3.4 50.5
V V mA
35
Dropout pulse, High level
VPDH
36
PB mode circuit current
IPB
H 5 42.44 3 A 2.41 4.08 2.51 4.23 2.61 4.38 V V
37
VG pin DC voltage
VG
- 13 -
100s OFF level ON level 5MHz 3.2V 0V
38
VREG pin DC voltage VREG
1 See the Control Logic Truth Table for control logic conditions. 2 Signal description of dropout detection.
ON, OFF level testing at Pin 18
Pin 12 input signal 100mVp-p
CXA1202Q-Z/CXA1202R
Pin 13 DOC PULSE
Control Logic Truth Table Operation of each section under respective input condition Recording Playback
Input condition and operation (Pin 39) RF SWP Operation Mode
Control Iogic input condition
(Pin 1) RP PB EN
(Pin 45) RP PB 1CH
(Pin 47) RP PB 2CH
(Pin 22) MULTl
(Pin 41) PCM SEL
(Pin 24) MIX1 OUT
(Pin 37) MIX2 OUT
(Pin 28) REC1 OUT
(Pin 33) REC2 OUT CH1 HEAD AMP
CH2 HEAD AMP
medium range freq. compensation circuit, DOC DET, RF SW
(Pin 8) PCM RF OUT (Pin 10) AGC OUT
Control Iogic condition -- V X X X X X X X O O X O O O O O O X X X CH2 CH1 X CH1 CH2 X X X X X X X X X X X CH1 CH2 X X X X X X X X X X X X X X X X X X X X V V V V P MP MP MP MP X X P V P X X X X X X X P V V P P V V V V V X V V V X V V V -- -- -- H L -- H L L L H -- -- L L H -- L L H H L L L L L L L L
A
H
L
L
(Pin 20) V RF OUT
VIDEO REC Power save VIDEO REC REC VIDEO * PCM REC MULTI PCM REC PB PB
B C D
L L L
L H L
L L H
- 14 - H L H V P X P O X O L H H MP MP MP X X O O H H H MP MP X MP O X O
E F
H H
L L
L L
G
H
L
L
H I
H H
H H
H H
J
H
L
H
K
H
H
L
O MUTE MUTE (No signal) O MUTE MUTE (No signal)
VIDEO * PCM PCM after recording
L
H
L
H
PCM after recording O MUTE MUTE (No signal) O MUTE MUTE (No signal) MULTI * PCM PCM after recording
CXA1202Q-Z/CXA1202R
M
H
H
L
CXA1202Q-Z/CXA1202R
1. Description of input condition "High" ... Control logic input, over 3V. "Low" .... Control logic input, under 1V. "--" ...... Independent of High, Low. 2. Description of operation mode O ......... Operating X ......... Not operating * In recording mode V ......... VIDEO signal is output. P ......... PCM signal is output. MP....... ATF signal that passed through fixed 6-dB AMP in mix circuit is output, mixed with PCM signal. * In playback mode CH1 ...... CH1 signal is output. CH2 ...... CH2 signal is output. MUTE ... MUTE is applied to PB VIDEO signal in PCM after recording; at the same time, RF AGC gain is held.
- 15 -
Electrical Characteristics Test Circuit
REC2 IN
IREC2 50 100 3.3 5.6 33p 51k 2.2k 22k 5.6 0.1 3.3 100
PB IN 2P
PB IN 1P
IREC1
50
22k MT Q 36 34 29 0.1 2.2k CH2 REC AMP 24 23 46dB CH2 HEAD AMP 9dB CONTROL LOGIC MTF MTQ 19 18 0.01 17 0.1 5.8k 150k 220p 100k RF IN B 0.047 13 47k 1 2 3 VG 0.1 0.1 0.1 0.01 7 4 8 10 5 6 9 11 12 50 DOC PULSE RF OUT 16 CH1 GCA DOC 15 DET A 14 RF DET AGC B RF SW 12dB 1 DOC DET VP1 VP2 -6dB SW SW BPF Mute PV MT1 MT2 6dB
Medium range freq. compensation
0.1 2.2k 8.2k 33p
35 33 30 25 32 31 28 27 26
MT F
0.33 0.22 0.22 0.33
REC1 IN
5V
Signal output pin (Test) Control logic pin MIX1 OUT 0.01 MULTI Control point of input manner and input level of signal to head AMP: input by attenuating 50 signal source to 1/50 as shown below. Input level is controlled at 1/50. Signal input pin (Input level control point) Signal source impedance: 50 Resistance accuracy: 1%
2.2k 0.1 CH1 REC AMP MT1 SW23
MIX2 OUT
37
SW38
MT 2 46dB CH1 HEAD AMP 9dB 20 V RF OUT 21 0.1 5.8k 22
38
RF SWP
39
40
PCM SEL
41
ME LEVEL BPF Video -6dB CH2 SW CH1
42
50 Signal source 49 PB IN 1P
SW42 PV VCA VCA
0.047
0.1
10
25k
5.8k
50
0.047
50
50 1k 150k
HCHG
CIN
AFM IN
Y IN
0.047
RP PB EN
CXA1202Q-Z/CXA1202R
VCC 5V
0.1
22
PCM RF OUT
IVCC
AGC OUT
RF IN A
- 16 -
CH2 VCA ME LEVEL ATF SW Normal VCA PCM MIX SW AMP 6dB VCA 6dB Multi 0.047 0.3V 3V 50
43
ATF LEVEL
44
SW44
RP PB 1CH
45
PB IN 2P
0.047
ATF IN
46
50
RP PB 2CH
47
0.01
PCM IN
48
50
CXA1202Q-Z/CXA1202R
Description of Operations The functional blocks, voltage supply and GND pins of CXA1202Q-Z and CXA1202R are configured as follows: Block name Mix AMP + SW section REC AMP section CH1 CH2 Head AMP section Medium range frq. compensation circuit + SW section RF AGC section RF SW section Dropout detecting section Control logic section Standard voltage supply section in IC (VREG, VG) Individual blocks are described in the following paragraphs. [Mix AMP + SW] Here, each of Y, Chroma, AFM, ATF and PCM signals is input at a prescribed input level so that they are mixed together internally to achieve an appropriate current value at the head, and output to MIX1 OUT pin (CH1 signal) and MIX2 OUT (CH2 signal) at a correct timing. Control is possible at ATF LEVEL pin (0 to 3dB at 0 to 5V, OPEN not allowed) when only the ATF recording level is to be increased as required, and at ME LEVEL pin (0 to 3dB at 0 to 5V, OPEN not allowed) when only the low range signal (Chroma + AFM + ATF) recording level is to be increased. In MULTI PCM mode, the ATF recording level is boosted by 6dB. In SW, the signal is output to MIX1 OUT and MIX2 OUT pins under control of the control logic section. [REC AMP] Mix AMP + SW output is input after it is converted into a suitable current by an external resistor, to drive the head. Adjustment of the external resistor makes it possible to set a gain and DC bias current to match that of the head. Feedback dumping is applied to inhibit head resonance (refer to the Application Circuit), and take care that capacitance coupling will not occur across the input and output. Control signals of RP PB EN, RP PB 1CH and RP PB 2CH permit power saving in the channels while recording (refer to the Control Logic Truth Table). Power saving of about 85mW is possible through a single channel. CH1 CH2 Voltage supply pin 7 27 34 27 34 7 7, 17 (Output emitter follower section) 7, 17 (Output emitter follower section) 7, 17 (Peak hold section) 7 7 GND pin 43 21 40 21 40 19 19 19 19 43 43
- 17 -
CXA1202Q-Z/CXA1202R
[Head AMP] The playback signal from the head is amplified with low noise and high gain. For example, the equivalent input noise level at 1MHz is 662pVrms/ Hz.1 In PB, the total input capacitance2 will be about 75pF. To inhibit resonance between this capacitance and the head inductance, a feedback dumping is incorporated. Connect a bypass capacitor for PB IN 1N and PB IN 2N pins between these pins and the rotary transformer Vcc. So far as this capacitor is over 0.2F, the low-Ievel frequency response does not deteriorate. Beside the 0.1F good frequency response capacitor connected to pin VREG, by adding a capacitor of over 10F, degradation of noise level at low range can be prevented. Take care not to allow capacitance coupling between PB output and Head AMP input. 1 and 2 See the next page. [Medium range frequency compensation circuit + SW] This corrects the frequency response of the PB signal. It is possible to set to and Q magnitude by means of the external resistance value of MT F and MTQ pins (refer to the F graph). The amount of boost may be adjusted through the external volumes of MT1 and MT2 pins (refer to the graph showing the effect of standard response MT2 pin voltage on the amount of boost). By controlling the control logic section, SW is changed over with the timing of RF SW (switching pulse), to output PCM RF signals and VIDEO RF signals. Mute is applicable to VIDEO RF signals during PCM after recording within the PCM recording area period. [RF AGC] The played back VIDEO RF signal are output here to achieve a constant level of 100mVp-p. The time constant for AGC is set by means of the resistance and capacitance external to AGC TC pin. At the input section of the detector a HPF with a cutoff frequency of about 1MHz is incorporated. This is to permit detection within the Y signal band. In PCM after recording, MUTE applies during the PCM recording area period to keep the gain on an unchanged level. [RF SW] Signals input to RF IN A and RF IN B pins are selected by means of HCHG control signals and output via the 12-dB amplifier to RF OUT pin. This switch is utilized for SP/LP head changeover when a 4-head system is employed. [Dropout detection] Dropout is detected here from RF signals of played-back VIDEO and dropout pulse is output. The time constant is set by means of the external resistance and capacitance external to DOC TC pin. The detection level is set in the interior with 400mVp-p input as standard to obtain optimum level. Use an external coupling capacitance value of input of 47pF to achieve HPF function. [Control Logic] The IC is controlled from this section as it will save power when circuit blocks are not in use. Therefore, power saving is automatically executed while all the power supplies are switched on. Many SWs are also available to switch inputs or outputs with complicated timing. Internal logic circuits to control them are provided. It is possible to achieve all possible combinations of inputs/outputs necessary for the basic operations by means of the 13 modes shown in the Control Logic Truth Table. L is set when the control logic pin is open. [Standard voltage supplies in the IC] VREG 4.2V and VG 2.5V are provided as the standard voltage supplies in the IC. - 18 -
CXA1202Q-Z/CXA1202R
1 (Reference) Test Method of Head AMP C/N (1) input signal Level -42.0dBm [signal source: 50] (generates a voltage of 100Vp-p at both ends of 1). (2) Signal injection circuit
50 49
1 Signal source B A
CXA1202Q-Z CXA1202R head AMP
Head inductance 1.55H
Winding ratio 3:5
Fig. 1 The signal is input from A and B in Fig. 1. The equipment used for the input is shown in Fig. 2.
BNC
51
1200
A 1 B
To drum GND
Notes) 1. A chip resistance is used for 1 (ordinary carbon resistance produces inductance.) 2. 49 is composed of 51/1200. Fig. 2
During signal
(3) SPECTRUM ANALYZER setting conditions: RBW: 10kHz VBW: 1Hz Sweep time: 500s Span: 500kHz
5MHz Span 500kHz
C/N
During shortcircuit between A - B
(4) Keep the medium range frequency compensation circuit flat. (Voltage of Pins MT1 and MT2 is made equal to that of Pin VREG) (5) Observe the output at Pin 20 V RF OUT. 2 The total input capacitance includes all capacitances of REC AMP, rotary transformer, shielding wire, etc., in addition to the input capacitance of the Head AMP alone (47pF). - 19 -
CH2 HEAD
CH1 HEAD
Application Circuit
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
27k 27k 22k 0.01 22k 0.1 2200 0.01 37 24 23 46dB 39 CH2 HEAD AMP 9dB CONTROL LOGIC MTF MTQ 19 100k DOC IN 47p VCC EF RF OUT 220p DOC TC RF IN B DTC144 3.9k AFM Trap 5.6k 15k PF EQ Half Trap 59 REC Y RF 5 REC C RF OUT 4.7k 1000p DTA144 150k 56k 10k DTA144 2 DOP 18 17 16 CH1 GCA DOC DET 15 14 13 0.01 1 2 3 VG Y IN VCC 100k 1000p VREG AGC TC AGC OUT AFM IN HCHG 7 11 C IN 4 8 10 12 5 6 9 DTC 144 A RF DET AGC B RF SW 10k DOC 0.022 PULSE 12dB VP1 VP2 -6dB SW SW BPF Mute PV MT1 MT2 6dB DOC DET
Medium range freq. compensation
VCC 0.1 22k 22k 0.1 0.1 VIDEO BLOCK 0.1 0.1 0.1
22k 0.1 MT Q REC2 IN REC2 OUT VCC 2CH PB IN 2P PB IN 2N PB IN 1N PB IN 1P REC1 OUT VCC 1CH MT F 26 25 REC1 IN 2200 36 34 29 33 31 30 28 27 35 32
22k 0.01
RF SWP PCM area MIX1 OUT
To servo To PCM To system contoller MIX2 OUT MT 2 46dB CH1 HEAD AMP 9dB 20 GND PB V RF OUT AMP 21 GND 1CH 22 MULTI RF SWP GND 2CH PCM SEL ME LEVEL BPF GND REC ATF LEVEL RP PB 1CH CH2 0.047 RP PB 2CH 6dB PCM IN 48 Multi 47 ATF IN ATF SW Normal VCA 46 VCA PCM MIX SW AMP 6dB VCA ME LEVEL 45 44 PV VCA VCA 43 42 Video -6dB CH2 SW CH1 41 40 38 22k MT1 47k CH2 REC AMP CH1 REC AMP
0.01
CXA1201M
17 DOC PULSE
To PCM
REC PCM PB PCM after recording area
22k
47k
CXA1200Q
AFM Trap
ATF Trap
LPF
3
PB C RF IN
10k
10k
AFM Trap
ATF Trap
RP PB EN
PCM RF OUT
10
0.047
0.1
0.047
GND
0.1
0.1
0.1
REG 5V
10
22
ATF BLOCK LPF LPF AFM BLOCK EQ BPF
0.047
RF IN A
PB Pilot IN
CXA1204Q
PBIN2
REC Pilot OUT
VCO OUT
REC RF
CX20137
- 20 -
470k DTA144 220k JOG : High Normal : Low JOG : High Normal : Low 24 7 8 44 2
C Trap
S.L.
60 PB Y RF
To system contoller
ME/MP ATF LEVEL MULTI
5V/0V
CXA1202Q-Z/CXA1202R
Countermeasure for drop out pulse in EE or editing mode. On a Virgin tape, drop out pulse shows with EE or editing mode in the absence of playback output. In such case CXA1201M holds AGC gain. This may cause image disturbance at the beginning of either recording or editing from EE mode. To prevent this inconvenience, a 0V signal in recording and 5V in playback, synchronized with the REC/PB signal of CXA1201M is entered. At 0V, the voltage of Pin 18 rises as if the input level for drop out detection had increased. This prevents the drop out pulse even if there is no signal.
Drop out countermeasures for virgin tape in playback. During playback of virgin tape, as drop out pulse is generated, drop out compensation is activated for long periods to deal with noise. V sync is disturbed and the picture loses its clarity. To prevent that, drop out pulse is passed through HPF and after continuation for a certain period the pulse disappears.
CXA1202Q-Z/CXA1202R
Precautions 1. Do not connect parasite capacitance to REC AMP dumping.
Recording current
C1
C1
Effect of C2 Effect of C1
C2 28 REC AMP 25
Frequency
2. Do not bring Head AMP input near PB output. Normally, there is a gain of 67dB between Head Amp input (Pins 29, 30) and RFOUT (Pin 16). During no signal, the gain is 74dB (as AGC reaches maximum gain). Bringing those closer on the pattern may cause oscillations in the vicinity of 6 to 7MHz. 3. Use 150k for RF AGC time constant, Resistance Because a change in this R causes a change in the AGC output level, change the time constant using the value of capacitance. 4. Watch the time constant of dropout detection.
VCC R1 DOC TC 15 R2 C
Time constant: t = C x (R1//R2) C: over 150pF R2 = 1.2 to 2.0V R1 + R2 Oscillations may occur unless this condition is satisfied. R1, R2: 5 x
5. Take AFM PB output from V RF OUT (Pin 20) Passing AFM signal through RF AGC causes AGC to reach maximum gain when playing back a virgin tape. As a result MUTE may not apply to AFM IC (CX20137, CX20037). 6. Adjust tape path by mixing V RE OUT signal and PCM RF OUT signal. In the absence of a signal before switching, observe the envelope comprising the combination of the VIDEO area and the PCM area by mixing outputs from V RF OUT (Pin 20) and PCM RF OUT (Pin 8).
RF SWP
V RF OUT
PCM RF OUT
After mixing
- 21 -
CXA1202Q-Z/CXA1202R
Mix AMP Chroma gain vs. ME LEVEL pin voltage
5 4
Mix AMP ATF gain vs. ATF LEVEL pin voltage
5 4
Gain [dB]
3 2 1
Gain [dB]
0 1 2 3 4 ME LEVEL pin voltage [V] 5
3 2 1
0
1 2 3 4 ATF LEVEL pin voltage [V]
5
Conditions: Input: Pin 2, 126mVp-p, 750kHz Output: Pin 24 Logic A
Conditions: Input: Pin 46, 250mVp-p, 100kHz Output: Pin 24 Logic A
Mix AMP Y output secondary distortion factor vs. Frequency
Secondary distortion factor [dB]
REC AMP frequency response
-40 -50 -60
Relative gain [dB]
2 4 6 8 f - Frequency [MHz] 10
5 0 -5 -10
0
2
4
6 8 10 12 14 16 18 20 f - Frequency [MHz]
Conditions: Input: Pin 6, 250mVp-p Output: Pin 37 Logic A
Conditions: Input: At resistance (2.2k) with Pin 25, 200mVp-p Output: Pin 28, load resistance: 100 Logic A
REC AMP secondary distortion factor vs. input level, output current
Secondary distortion factor [dB]
REC AMP distortion factor vs. Frequency
-40 -50 -60
Distortion factoc [dB]
-40 -50 Second -60 Third
Input level Output current
-16-14-12-10 -8 -6 -4 6 8 10 1315 20
0 [dBm] [mAp-p]
2
4 6 8 f - Frequency [MHz]
10
Conditions: Input: At resistance (2.2k) with Pin 25, 5MHz Output: Pin 28, load resistance: 100 Logic A
Conditions: Input: At resistance (2.2k) with Pin 25, 200mVp-p Output: Pin 28, load resistance: 100 Logic A
- 22 -
CXA1202Q-Z/CXA1202R
Head AMP output level vs. Frequency
Change in output level [dB]
V RF OUT secondary distortion factor vs. Input level
Secondary distortion factor [dB]
5 0 -5
-40 -50 -60
2
4 6 8 f - Frequency [MHz]
10
-6 -4 -2 0 2 4 6 Input level [dB]
8 10 12
Conditions: Input: 25m-wide head for NTSC, 100mVp-p at head tip Output: Pin 20 Logic H, medium range freq. conpensation circuit boost: 0
Conditions: Input: Pin 29, 0dB = 200mVp-p, 5MHz Output: Pin 20 Logic H
CH1 CH2 crosstalk at RF OUT vs. Frequency
CH1 CH2 crosstalk at PCM RF OUT vs. Frequency
Crosstalk [dB]
Crosstalk [dB]
2 4 6 8 f - Frequency [MHz] 29 20 32 0.1F
-30 -40 -50
-30 -40 -50
Crosstalk
Conditions: Input: Pin 29, 200Vp-p Output: Pin 20 Logic I
4 6 8 f - Frequency [MHz] Conditions: Input: Pin 29, 200Vp-p 29 Output: Pin 8 Logic H 32 0.1F
2
Crosstalk 2
Crosstalk in MUTE at V RF OUT vs. Frequency
Medium range freq. compensation circuit MT2 pin voltage vs. Amount of boost
Amount of boost [dB]
Crosstalk [dB]
-50 -60 -70
14 12 10 8 6 4 2 0
2
4 6 8 f - Frequency [MHz] 29
10 Crosstalk 20
1
2 3 4 MT2 pin voltage [V]
5
Conditions: Input: Pin 29, 200Vp-p Output: Pin 20 Pin 41 voltage: 5V Logic H
Conditions: MT F pin: 18k MT Q pin: 33k
- 23 -
CXA1202Q-Z/CXA1202R
Medium range freq. compensation circuit MT F, MT Q pin connection resistance value vs. F
12 MT Q pin connection resistance value [k] 10
Medium range freq. compensation circuit MT F, MT Q pin connection resistance value vs. Q
MT Q pin connection resistance value [k] 4.0 10 3.0 15 22 33 47 68
F [MHz]
8 6 4 2 10 15 22 33 47 68
Q
2.0 1.0 20 40 60 80 MT F pin connection resistance value [k] 20 40 60 80 MT F pin connection resistance value [k]
Medium range freq. compensation circuit boost amount vs. Operating temperature
Medium range freq. compensation circuit F, vs. Operating temperature
Amount of boost [dB]
Change in F [kHz]
Conditions: Input: Pin 29 Output: Pin 20 Pin 23 voltage: 4.2V Logic H
200 100 0 -100 -200
13 12 11 10
-20 0 20 40 60 80 Topr - Operating temperature [C]
-20 0 20 40 60 80 Topr - Operating temperature [C] Conditions: Input: Pin 29 Output: Pin 20 Pin 23 voltage: 4.2V Q pin connection resistance value: 33k F pin connection resistance value: 18k
RF AGC Control characteristics
0dB = 100mVp-p Output level [dB]
AGC output level vs. Operating temperature
Difference in output level [dB]
150k 9 1 0 -1 VCC 0.047F
2 1 0 -1 -2 -3 -4 -5 -6 -16-12 -8 -4 0 4 8 12 16 18 0dB = head tip, 100Vp-p [dB]
-20 0 20 40 60 80 Topr - Operating temperature [C] Conditions: Input: Pin 29, 5MHz, 170Vp-p Output: Pin 10 Logic H
Conditions: Input: 25m-wide head for NTSC, 5MHz Output: Pin 10 Logic I Pin 9 time constant: R: 150k, C = 0.047F
- 24 -
CXA1202Q-Z/CXA1202R
Dropout detection ON level vs. Operating temperature
VCC 150k 15 100k -10 -11 -12 -13 -14 -15 -20 0 20 40 60 80 Topr - Operating temperature [C] Conditions: Input: Pin 14 400mVp-p to 0dB at Pin 16 Logic H
Dropout detection OFF level vs. Operating temperature
VCC 150k 15
OFF level [dB]
ON level [dB]
220pF
100k -4 -5 -6 -7 -8 -9
220pF
-20 0 20 40 60 80 Topr - Operating temperature [C] Conditions: Input: Pin 14 400mVp-p to 0dB at Pin 16 Logic H
RF SW Crosstalk (A B) vs. Frequency
Crosstalk [dB]
0 -10 -20 -30 -40 -50 -60 2 4 6 8 f - Frequency [MHz] 10 Crosstalk 16 14 0.01 0.01 12
Conditions: Input: Pin 12, 100mVp-p Output: Pin 16 Logic H Pin 11 = 3V
- 25 -
CXA1202Q-Z/CXA1202R
Package Outline
Unit: mm
CXA1202Q-Z
15.3 0.4 + 0.4 12.0 - 0.1
48PIN QFP (PLASTIC)
+ 0.1 0.15 - 0.05 0.15
36
25
37
24
48
13
+ 0.2 0.1 - 0.1
1 + 0.15 0.3 - 0.1
12
0.8
0.24
M
+ 0.35 2.2 - 0.15
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-48P-L04 QFP048-P-1212 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER / PALLADIUM PLATING 42/COPPER ALLOY 0.7g
NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).
CXA1202R
9.0 0.2 36 37 7.0 0.1 25
48PIN LQFP (PLASTIC)
24
(8.0)
A 48 1 0.5 + 0.08 0.18 - 0.03 + 0.2 1.5 - 0.1 12 13
(0.22)
+ 0.05 0.127 - 0.02 0.13 M 0.1
0.1 0.1
0 to 10
0.5 0.2
NOTE: Dimension "" does not include mold protrusion.
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-48P-L01 LQFP048-P-0707 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER/PALLADIUM PLATING 42/COPPER ALLOY 0.2g
- 26 -
0.5 0.2
0.9 0.2
13.5

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